This application claims the priority of Korean Patent Application No. 2003-22210, filed on Apr. 9, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a lateral double-diffused MOS transistor, and more particularly, to a lateral double-diffused MOS transistor having multiple current paths for a high breakdown voltage and a low on-resistance.
2. Description of the Related Art
In general, high-voltage integrated circuits (ICs) in which at least one high-voltage transistor is arranged on the same chip together with low-voltage circuits are widely used in a variety of electrical applications. In these ICs, a lateral double-diffused MOS (LDMOS) transistor is an important high-voltage device. It is well-known to design LDMOS transistorsby, minimizing on-resistance while maintaining a high breakdown voltage. However, it is also well-known that low on-resistance and high breakdown voltage parameters are contradictory to each other in current process technologies.
A technology for increasing a breakdown voltage while maintaining a low on-resistance is reduced surface field (RESURF) technology. In addition, in order to obtain an increase in a breakdown voltage and a reduction in an on-resistance more efficiently, a structure having a field shaping layer isalso known. According to the RESURF technology, by reducing the thickness of an epitaxial layer and simultaneously increasing the doping concentration of the epitaxial layer slightly, a high breakdown voltage and a desired on-resistance can be obtained. By redistributing a field density inside a LDMOS transistor, a low on-resistance can be obtained in the field shaping layer. The more the field shaping, the lower the on-resistance of the LDMOS transistor.
FIG. 1 is a cross-sectional view illustrating a structure of a conventional LDMOS transistor in which a RESURF technology and a field shaping layer are introduced.
Referring to FIG. 1, an n−-type epitaxial layer 104 is arranged on a p−-type semiconductor substrate 102. The n−-type epitaxial layer 104 is used as a drift region. A p-type buried layer 106 is arranged in a part of region of a boundary between the p−-type semiconductor substrate 102 and the n−-type epitaxial layer 104. A p−-type well region 108 is formed in a predetermined upper region of the n−-type epitaxial layer 104. A lower portion of the p−-type well region 108 may be overlapped with a lower portion of the p-type buried layer 106. An n+-type source region 110 and a p+-type source contact region 112 are arranged in a predetermined upper region of the p−-type well region 108. Meanwhile, an n+-type drain region 114 is arranged in the predetermined upper region of the n−-type epitaxial layer 104 to be spaced apart from the p−-type well region 108 by a predetermined gap.
A p-type field shaping layer 116 is arranged between the p−-type well region 108 and the n+-type drain region 114. The p-type field shaping layer 116 is spaced a predetermined distancefrom the p−-type well region 108 and the n+-type drain region 114, respectively. A gate insulating layer 120 is arranged on a channel region 118, and a gate electrode 122 is arranged on the gate insulating layer 120. A source electrode 124 is formed to be electrically connected to the n+-type source region 110 and the p+-type source contact region 112. A drain electrode 126 is formed to be electrically connected to the n+-type drain region 114. The gate electrode 122, the source electrode 124, and the drain electrode 126 are electrically insulated from one another by an interlevel dielectric (ILD) layer 128.
In such a LDMOS transistor, the p-type field shaping layer 116 distributes the field inside the LDMOS transistor uniformly together with the p-type buried layer 106, such that field concentration in a bended junction portion is alleviated, breakdown voltage is increased and the stability of a device is improved. However, due to a limited current path (indicated by arrow in FIG. 1) composed of the channel region 118 and a lower portion of the p-type field shaping layer 116, an overall current transport ability is lowered, and since the p-type field shaping layer 116 is placed in the surface of the n−-type drift region 116, the static on-resistance is high.